The general structures and manufacturing processes for electronic packages are described in, for example, Donald P. Seraphim, Ronald Lasky, and Che-Yo Li, Principles of Electronic Packaging, McGraw-Hill Book Company, New York, N.Y., (1988), and Rao R. Tummala and Eugene J. Rymaszewski, Microelectronic Packaging Handbook, Van Nostrand Reinhold, New York, New York (1988), both of which are hereby incorporated herein by reference.
As described by Seraphim et al., and Tummala et al., an electronic circuit contains many individual electronic circuit components, e.g., thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components are interconnected to form the circuits, and the individual circuits are further interconnected to form functional units. Power and signal distribution are done through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function, and the removal of thermal energy to remain functional. Microelectronic packages, such as, chips, modules, circuit cards, circuit boards, and combinations thereof, are used to protect, house, cool, and interconnect circuit components and circuits.
Within a single integrated circuit, circuit component to circuit component and circuit to circuit interconnection, heat dissipation, and mechanical protection are provided by an integrated circuit chip. This chip is referred to as the "zeroth" level of packaging, while the chip enclosed within its module is referred to as the first level of packaging.
There is at least one further level of packaging. The second level of packaging is the circuit card. A circuit card performs at least four functions. First, the circuit card is employed because the total required circuit or bit count to perform a desired function exceeds the bit count of the first level package, i.e., the chip or module. Second, the circuit card provides for signal interconnection with other circuit elements. Third, the second level package, i.e., the circuit card, provides a site for components that are not readily integrated into the first level package, i.e., the chip or module. These components include, e.g., capacitors, precision resistors, inductors, electromechanical switches, optical couplers, and the like. Fourth, the second level package provides for thermal management, i.e., heat dissipation.
Packages may be characterized by the material used as the dielectric, i.e., as ceramic packages or as polymeric packages. The basic process for polymer based composite package fabrication is described by George P. Schmitt, Bernd K. Appelt and Jeffrey T. Gotro, "Polymers and Polymer Based Composites for Electronic Applications" in Seraphim, Lasky, and Li, Principles of Electronic Packaging, pages 334-371, previously incorporated herein by reference, and by Donald P. Seraphim, Donald E. Barr, William T. Chen, George P. Schmitt, and Rao R. Tummala, "Printed Circuit Board Packaging" in Tummala and Rymaszewski, Microelectronics Packaging Handbook, pages 853-922, also previously incorporated herein by reference.
In the normal process for package fabrication a fibrous body, such as a non-woven mat or woven web, is impregnated with a resin. This step includes coating the fibrous body with, for example, an epoxy resin solution, evaporating the solvents associated with the resin, and partially curing the resin. The partially cured resin is called a B-stage resin. The body of fibrous material and B stage resin is called a prepreg. The prepreg, which is easily handled and stable, may be cut into sheets for subsequent processing.
Typical resins used to form the prepreg include epoxy resins, cyanate ester resins, polyimides, hydrocarbon based resins, and fluoropolymers. One such composite material is a composite of glass fibers and PTFE-type polymeric materials.
The polymeric dielectric is processed to form an adherent surface for circuitization, and to accommodate vias and through holes. Circuitization is applied after surface preparation and hole drilling.
Subsequent processing of polymeric substrates includes circuitization, that is, the formation of a Cu signal pattern or power pattern on the prepreg, or lamination of the prepreg to a power core. Circuitization may be additive or subtractive.
In the case of additive circuitization a thin film of an adhesion layer, such as a thin film of chromium, is first applied to the prepreg or polymeric dielectric. The adhesion layer may be applied by sputtering. Typically, the film of adhesion metal is from about 500 Angstroms to about 2000 Angstroms. Thicker layers of chromium result in internal streses, while thinner layers may be non-continuous.
Thereafter a "seed" layer of copper is applied atop the adhesion layer. This copper layer is from about 3000 Angstroms thick to about 25,000 Angstroms (2.5 microns) thick. It may be applied by sputtering, evaporation, electrodeposition, or electroless deposition.
Subsequently, photoresist is applied atop the copper "seed" layer, imaged, and developed to provide a pattern for circuit deposition. Copper circuitization is then plated onto the exposed copper "seed" layer to provide the circuitization pattern on the surface of the package. The remaining photoresist is then stripped, leaving a thick copper plated circuitization pattern and a thin multilayer "background" of a "seed" copper layer and a chromium adhesion layer.
The resulting circuitized prepreg is called a core. The composite printed circuit package is fabricated by interleaving cores (including signal cores, signal/signal cores, power cores, power/power cores, and signal/power cores) with additional sheets of prepreg, and surface circuitization. Holes, as vias and through holes, may be drilled in individual core structures, for example, before or after circuitization, as described above, or in partially laminated modules.
The multi-layer structure of cores and planes in a multi-layer package requires vias and through holes to accommodate vertical circuitization. Vias and through holes are formed in the polymeric dielectric to accommodate this required vertical circuitization in multilayer packages. In the formation of vias and through holes, for example, by laser ablation in glass filled polymer dielectrics, dielectric debris is deposited within and around the vias and through holes. In the case of hydrocarbon polymer dielectrics, as polyimide dielectrics, this debris can be readily removed by plasma etching.
However, both glass fibers and PTFE-type polymers are especially resistant to plasma etching processes. Moreover, the debris is highly adherent to the the via and through hole walls, so that weak fluid rinses are ineffective in removing them. Stronger fluids, as HF, that are strong enough to remove the debris can cause degradation of the polymeric dielectric material beyond the narrow bounds of the via or through hole. Thus a need exists for an efficient, effective means of removing debris generated during excimer laser drilling from vias and through holes.